The Comparative Analysis of Power Optimization in Clustered Sleep Transistors

Abstract

This paper concentrates on the various power reduction techniques for clustered sleep transistors and in particular leakage and dynamic power of the gated circuits published recently based on different logic styles. All the advantages and applications of the circuits have discussed with the relevant proofs of results and analytical models. All the circuits are designed and tested using spice simulation models and the screenshots of the different sleep transistor circuits based on Multi-threshold CMOS approach have depicted and its advantages over other methodologies have tested and its spice simulation results has presented with the required analytical model and the final layout of clustered sleep transistor has laid down.